RTL PCIe Lead Engineer
Spain
Permanent
Salary DOE
Description
Are you passionate about microprocessor architecture and ready to take a crucial role in designing high-performance semiconductor solutions?
Join our High-Speed IO Team as a PCIe Lead Engineer!
You will be responsible for defining the architecture and leading the RTL implementation of PCIe solutions.
A key focus will be ensuring optimal interaction between the PCIe subsystem and our cores, which utilize the AMBA-CHI protocol for coherency.
Your expertise in PCIe integration and/or design will be essential to create the efficient, high-performance subsystems vital for modern semiconductor designs.
You will collaborate closely with other highly skilled engineers across multiple teams.
Requirements
* Industrial experience +8 years
* Proven experience of PCIe, in design or integration of PCIe solutions.
* Proven experience in design and/or integration of IPs in a SoC/ASIC environment.
* Experience in at least one of the following protocols: AXI, CHI, AHB.
* Proficiency in RTL design using Verilog or VHDL.
* Experience with basic block level testing.
Desired
* Master or PhD.
* Knowledge of C++ and/or scripting languages (Python, Perl, Bash, TCL).
* Knowledge of revision control methodology and tools (git, svn).
* Knowledge of coherency concepts and protocols.
* Experience in CXL.
* Experience in common tools used in digital design (Synthesis, Timing, CDC, Lint, etc…)
If you would like to learn more, please email
#J-18808-Ljbffr