ROLE: Senior Verification Engineer
LOCATION: Barcelona, Spain
SALARY: Negotiable
DURATION: Permanent
Description:
We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise in digital design verification. The adecuado candidate will have a strong background in SystemVerilog and UVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge of both formal and dynamic verification methodologies is essential.
In this role, you will work within the Verification Team to ensure the correctness and functionality of complex microprocessor architectures at the RTL level. You will develop and apply advanced verification methodologies, build testbenches, run simulations, and collaborate closely with design teams to deliver high-quality, production-ready designs.
Requirements:
- Master's or PhD in Computer Science, Electrical Engineering, or a related field
- Proficiency in SystemVerilog and UVM
- Strong scripting skills (Python, Perl, Bash, Tcl)
- 8+ years of relevant industry experience
- Hands-on experience with simulation tools and regression management
- Familiarity with revision control tools (git, svn)
- Proven experience in block-level, subsystem, and top-level verification
- Background in both formal and dynamic verification methodologies
- Excellent problem-solving skills and attention to detail
- Strong communication and teamwork abilities
- Proficiency in English (C1 level)