PbJob Title /b /ppSenior Mixed-Signal IC Design Engineer /ppbLocation /b /ppMadrid, Spain (Tres Cantos) – with flexibility for remote working depending on profile /ppbCompany Overview /b /ppA cutting-edge semiconductor and technology company focused on the design and development of advanced mixed-signal and high-performance IC solutions. /ppThe organisation operates at the forefront of innovation, developing complex integrated systems combining analog, digital, and optoelectronic technologies within deep submicron CMOS nodes. The team is highly collaborative, research-driven, and focused on delivering next-generation products for demanding applications. /ppbRole Overview /b /ppThe company is looking for a Senior Mixed-Signal IC Design Engineer to contribute to the specification, design, and validation of advanced analog and mixed-signal blocks within complex SoCs. /ppThis role involves full ownership across the AMS design flow, working closely with system, layout, and test teams, while contributing to product innovation and future architecture development. /ppbKey Responsibilities /b /pulliDefine specifications for analog and mixed-signal blocks (ADC, DAC, PLLs, interfaces, optoelectronic modules) /liliDesign and verify AMS circuits in deep submicron CMOS (65nm / 28nm and below) /liliOwn full design flow: system-level modelling, schematic design, layout supervision, and post-layout verification /liliProvide layout guidelines and review physical implementation /liliCollaborate with test engineers on silicon validation, characterization, and correlation with simulations /liliSupport system-level modelling and integration into complex mixed-signal SoCs /liliContribute to mixed-signal verification alongside digital teams /liliResearch new architectures and contribute to IP / patent generation /liliPresent technical work and contribute to internal knowledge sharing /li /ulpbRequirements /b /pulliMSc or PhD in Electronics, Electrical Engineering, or related field /lili~5+ years’ experience in Analog / Mixed-Signal IC design /liliProven experience delivering designs into silicon (definition → validation → production) /liliStrong experience with Cadence / Synopsys design tools /liliHands-on experience designing in sub-nanometer CMOS nodes (≤65nm) /liliSolid understanding of full-custom analog layout and ability to review layout work /liliStrong communication skills and ability to work in cross-functional teams /liliFluent in English /li /ulpbNice to Have /b /pulliExperience with complex mixed-signal SoC integration /liliExposure to optoelectronics or interface design /liliExperience with behavioural modelling /liliBackground contributing to innovative architectures or patent development /liliExperience mentoring or guiding junior engineers /li /ulpbSalary Package /b /ppCompetitive and aligned with experience within an innovative semiconductor environment /p