Design Verification Engineer
A leading semiconductor powerhouse in Barcelona, Spain is looking for a Design Verification Engineer Contractors to join their exciting new market-leading team on a permanent basis.
Successful candidates will deploy industry-leading verification methodologies such as UVM, and develop testbenches and verification components such as UVCs.
Required:
ASIC Design Verification, UVM-based functional verification, or related.UVM, System Verilog, Perl/Python shell scripting skills.
Desired:
Jasper or VC Formal Verification Tools.SystemC and Matlab Experience.Familiarity with C/C++
Key words: Design / Verification / ASIC / UVM / Testbench / Systemverilog / Matlab / Python / Perl / Jasper / SystemC / Semiconductor /
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