Job Title: UVM / PCIe Verification Engineer (Contract)
Contract Length: 6 Months
Location: Barcelona, Spain
Work Model: Hybrid / Remote Available
Eligibility: EU Candidates Only
Overview
We are looking for an experienced UVM / PCIe Verification Engineer to join a leading technology client based in Barcelona on a 6-month contract.
The successful candidate will work as part of a high-performing verification team responsible for ensuring the quality and functionality of complex high-speed digital interfaces, with a focus on PCIe verification using UVM methodology.
This role offers flexibility with hybrid or remote working options, while collaborating with an international engineering team.
Key Responsibilities
* Develop and maintain UVM-based verification environments for complex digital designs
* Verify PCIe-based IP and subsystems to ensure compliance with specifications and performance requirements
* Create and execute test plans, test cases, and verification strategies
* Perform functional and protocol-level verification of high-speed interfaces
* Develop SystemVerilog testbenches and verification components
* Analyse simulation results and debug design and verification issues
* Work closely with design, architecture, and integration teams to ensure verification coverage and product quality
* Contribute to coverage closure and regression testing
Required Skills & Experience
* Strong experience in SystemVerilog and UVM verification methodology
* Proven experience verifying PCIe (PCI Express) interfaces or IP
* Experience building UVM testbenches, sequences, scoreboards, and monitors
* Solid understanding of digital design and verification principles
* Experience with functional coverage and constrained random verification
* Strong debugging and problem-solving skills
* Ability to work effectively in distributed and international teams
Preferred / Nice to Have
* Experience with high-speed interface verification (PCIe Gen4/Gen5 preferred)
* Knowledge of verification planning and coverage methodologies
* Experience with EDA simulation tools (e.g., Synopsys, Cadence, Siemens/Mentor)
* Experience working on SoC or IP-level verification