Locations: Europe (Germany / France / Switzerland / Netherlands)
The CompanyJoin a well-funded, early-stage AI hardware company building next-generation compute systems to dramatically improve AI inference efficiency.
They sit at the intersection of semiconductor design, in-memory computing, and compiler infrastructure, with a strong hardware–software co-design focus across edge-to-cloud environments.
The RoleCore hire within the compiler team, focused on building and optimising graph compiler infrastructure for custom AI accelerators.
You'll work closely with hardware architects and ML researchers, shaping how models are lowered, optimised, and executed on novel architectures.
Strong focus on MLIR / graph compilers and end-to-end performance optimisation.
Optimise graph compiler passes for AI workloads
Lower models (PyTorch / TensorFlow) into efficient IR
Drive graph-level optimisations (fusion, tiling, scheduling)
Collaborate with hardware teams on accelerator-aware design
Contribute to IR design and compiler infrastructure
Experience in compiler engineering (AI / ML compilers preferred)
MLIR, Torch-FX, TVM or similar
Understanding of GPU / ASIC / accelerator architectures
Strong C++ and/or Python
Experience in performance optimisation / codegen
Working on first-of-a-kind hardware where the compiler is central to unlocking performance — not an afterthought.
#J-18808-Ljbffr