We seek an experienced place-and-route engineer to manage complex digital backend flows. The role requires interfacing digital front-end designers to understand the requirements that come from RTL synthesis and to be able to partition architectures to give inputs at the generation of rational floorplanning and to drive physical aspects early in the design cycle.
Responsibilities:
* Assure the deliverability of the main part of the chip;
* Take care of P&R/STA flows and tools available in the latest industry;
* Understand the meaning of the synthesis and capability to drive place and route of complex blocks through signoff flows including timing and physical verification;
* Drive Place & Route in chip-level and hierarchical physical implementation environment taking care of the floorplan with a critical mind;
* Run MBIST and DFT insertion into blocks, understanding the impact of MBIST/Scan and debug logic is desirable;
* Continue interaction with RTL designers to resolve design issues on block closure and assure power/performance/area targets.
Qualifications:
* Master’s degree in Electrical Engineering, Electronics Engineering or 7+ years of experience in the field;
* Experience in physical design flow including gate level netlist, floor planning, partitioning, power planning, placement, synthesis, clock & power distribution, timing closure, and routing;
* DRC/LVS and parasitic extraction capability.
The person should be located in Barcelona or Italy.
We are looking for team players who focus on the outcome of the team above the individual needs, with respect and honest challenge. Within- and cross-team collaboration at the technical level is essential. The ideal candidate should have a “can-do attitude”, willing to solve any obstacle independently, and be self-starter and self-motivated.
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