Research Engineer - RTL OoO Core Development (RE2)
Location: Barcelona Supercomputing Center, Computer Sciences Department, Barcelona, Spain
Job Reference: 729_25_CS_CORE_RE2
Closing Date: Saturday, 13 December 2025
About BSC
The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing centre in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries.
Role Overview
In the Computer Architecture research group, we are working on designing and developing a high-end out‑of‑order processor for the HPC Zettascale Laboratory. We are seeking a highly skilled and experienced Senior RTL Engineer to join our team in maintaining and optimizing a current high‑performance Out‑of‑Order (OoO) CPU. This role involves developing robust, efficient, and scalable RTL implementations for advanced microarchitectural features, contributing to the next generation of cutting‑edge processor designs.
Key Duties
* Research computer architectural techniques and develop RTL hardware structures related to superscalar OoO core design to improve efficiency, scalability, and performance of a current RISC‑V core.
* Review and analyze state‑of‑the‑art performance techniques for OoO processor architectures to identify the most effective approaches.
* Design RTL structures by implementing the selected techniques for RISC‑V CPU architectures. Implement complex control logic, data paths, and microarchitectural features in SystemVerilog.
* Integrate new capabilities into RISC‑V Core, providing an efficient and configurable means of RISC‑V processor cores with trade‑off balance with performance improvements.
* Develop a verification strategy with CoCoTB for derived modules and Python hardware modeling. Implement verification tests and validation procedures to ensure correctness and functionality.
* Evaluate performance impact of new capabilities through extensive simulation and benchmarking. Measure improvements in terms of execution efficiency, reduced cycle count, and overall performance.
* Follow methodology and quality standards for code base development.
* Document design specifications, micro‑architecture, and test plans. Prepare reports and presentations on design progress, issues, and metrics.
* Develop and maintain scripts and tools to automate design and verification tasks. Contribute to improvement of design and verification methodologies within team.
* Ensure high‑quality, maintainable, and reusable RTL code. Perform code reviews and provide constructive feedback to peers.
* Ensure design compliance with industry standards and best practices. Follow project‑specific guidelines and contribute to establishment of new standards.
Requirements
* Education: BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering.
* Essential Knowledge and Professional Experience:
o Logic Circuit Design Knowledge.
o Proficiency in SystemVerilog.
o Computer Architecture Knowledge.
o Familiarity with RISC‑V Specification.
o Git version control system Knowledge.
o Python and CoCoTB experience.
o Proficiency with standard open‑source and industry tools for RTL simulation.
o Direct Programming Interface for HW Modeling and Host Interfacing.
o Make, Bash, Docker.
* Additional Knowledge and Professional Experience:
o Programming experience with C, C++.
o Experience working with Linux operating system.
* Competences:
o Good English communication skills (written and speaking).
o Teamwork and collaboration.
o Assertive communication.
o Adaptability.
o Problem‑solving.
o Critical thinking.
o Time management.
o Interpersonal skills.
o Attention to detail.
Conditions
* Position will be located at BSC within the Computer Sciences Department.
* Full‑time contract (37.5h/week), flexible working hours, extensive training plan, restaurant tickets, private health insurance, relocation support.
* Duration: Open‑ended due to project and budget duration.
* Holidays: 22 days + 6 personal days + 24th and 31st of December per collective agreement.
* Salary: Competitive, commensurate with qualifications, experience and cost of living.
* Starting date: Month 0.
Applications Procedure
All applications must be submitted via the BSC website and contain:
* A full CV in English including contact details.
* A cover/motivation letter with statement of interest in English, specifying areas/topics you wish to be considered. Two references for further contacts must be included.
EEO Statement
BSC‑CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.
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