**Job Reference**:
- 646_25_CS_V_RE3
**Position**:
- SoC DV engineer (RE3)
**Closing Date**:
- Tuesday, 11 November, 2025
**Reference**: 646_25_CS_V_RE3
**Job title**: SoC DV engineer (RE3)
**About BSC**
- The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D; into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries.
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**Context And Mission**
- DARE European Supercomputing Project.
BSC is looking for talented and motivated professionals with expertise in Design Verification for a European HPC accelerator in the context of the DARE Project and other related research projects. The design is based on RISC-V architecture. BSC contributes a RISC-V vector accelerator, scalar RISC-V cores and components of the cache hierarchy and integrates all the components: verifying functional correctness at the system level is key for success of the project.
**Key Duties**
- You will use your design and verification expertise to verify complex digital designs, focused on scalar processors, caches and coherency protocol components.
- You will be involved in the verification at the SoC level, and will use your experience integrating VIP to verify coherence protocol components of the design and its integration.
- You will collaborate closely with design and verification engineers in active projects and perform hands-on verification, and contribute to design, build, and integrate the designs.
- Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise the designs through their corner-cases and expose all types of bugs.
- You will be responsible for the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.
- You will train others in the configuration, deployment, use and/or maintenance of verification software, scripts and workflows.
- You supervise, guide and coordinate the work of less experienced Verification engineers working in the project.
- You will define and implement coverage plans for the design, and analyse the code and functional coverage results obtained to identify verification holes and to show progress towards tape-out.
**Requirements**:
- Education
- BS or MS degree in Electrical Engineering, Computer Engineering, or equivalent, with demonstrable professional experience.
- Essential Knowledge and Professional Experience
- Experience with the full verification life cycle from test planning to sign-off, at least 5 years of professional experience in verification.
- Substantial working knowledge of Universal Verification Methodology (UVM), writing test plans, simulating, debugging, and documenting results
- Extensive knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
- Significant experience in the following key DV methodologies: UVM, cosimulation, SystemVerilog Assertions, functional coverage, Assembly/C-based random/constrained-random Verification, Verification IPs.
- Strong experience in integrating VIP (e.g. AXI, PCIe) in an existing UVM testbench, configuring it correctly to match the DUT requirements and verification goals, and developing tests based on it.
- Experience in verification at the SoC level.
- Experienced in developing a DV plan based on Functional Specification, create and build the necessary verification test bench/infrastructure, develop tests and verify the design.
- Experience in the creation and implementation of validation plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Experience defining and implementing functional coverage, working with cross functional teams (DV/Arch/Design).
- Strong debugging and triaging skills and ability to work with design engineers to deliver functionally correct design blocks, execute tests, analyze data, and prepare reports summarizing results and stati