Organisation/Company UNIVERSIDAD POLITECNICA DE MADRID Department HRS4R Research Field Engineering » Electronic engineering Researcher Profile First Stage Researcher (R1) Positions Bachelor Positions Application Deadline 10 Mar 2026 - 23:00 (Europe/Madrid) Country Spain Type of Contract Temporary Job Status Part-time Hours Per Week 30 Offer Starting Date 24 Feb 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No
Offer Description
Responsibilities
* Design of CMOS oscillators in the sub-terahertz band.
* Design and testing of analogue CMOS circuits.
* Validation, verification and testing of chiplets for heterogeneous integration.
* RF (radio frequency) design and testing.
Where to apply
E-mail marta.ferreras@upm.es
Requirements
Research Field Engineering » Other Education Level Bachelor Degree or equivalent
Research Field Computer science » Other Education Level Bachelor Degree or equivalent
Skills/Qualifications
Students of a master degree on Electrical and Electronics Engineering, Telecommunication or similar.
Specific Requirements
* Background on design of mixed-signal circuits.
* Valuable Knowledge of commercial design tools like Cadence / Synopsys.
* Competence in computer architectures and digital system design with HDLs (Verilog or VHDL).
* Knowledge heterogeneous integration or chiplet design.
* Currently, pursuing a master's degree with specific content on electronic design, the work can be used as Master thesis at the end of the 25-26 academic year.
Languages ENGLISH Level Excellent
Languages SPANISH Level Excellent
Research Field Other Years of Research Experience 1 - 4
Additional Information
The contracted researcher will participate in a joint program with INDRA, an international Spanish-based company, within the project “Chair UPM-INDRA in microelectronics”.
Continuous training in mixed-signal and RF circuit design.
Eligibility criteria
* Academic records at bachelor's level.
* Previous experience in the design of electronic circuits.
* Level of compliance with the specific requirements.
Selection process
Additional comments
#J-18808-Ljbffr