A leading semiconductor powerhouse in Barcelona, Spain is looking for a Design Verification Engineer Contractors to join their exciting new market-leading team on a permanent basis.Successful candidates will deploy industry-leading verification methodologies such as UVM, and develop testbenches and verification components such as UVCs.Required:ASIC Design Verification, UVM-based functional verification, or related.UVM, System Verilog, Perl/Python shell scripting skills.Jasper or VC Formal Verification Tools.SystemC and Matlab Experience.Familiarity with C/C++Key words: Design / Verification / ASIC / UVM / Testbench / Systemverilog / Matlab / Python / Perl / Jasper / SystemC / Semiconductor /By applying to this role you understand that we may collect your personal data and store and process it on our systems.For more information please see our Privacy Notice.#J-*****-Ljbffr