You will join the receiving team to lead FPGA/SoC based hardware design projects, architecture definition, junior team mentoring and critical system optimization.
Developing functions:
- Architecture definition
- Coding in VHDL/Verilog
- Advanced verification (SystemVerilog/UVM)
- Resource optimization
- HW/SW interfaces definition
- Mentoring of junior engineers
- Technical documentation.
WHAT DO WE NEED IN OUR TEAM?
For this position, we are looking for hardware engineering experts with experience in FPGA development, advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim), modular/IP design, timing optimization, high speed interfaces, C++ or Rust, Python, GIT.
Knowledge of Process Automation, signal processing, HDL coder, soft core processors, standards (DO-254, ECSS), ASIC design would be an asset.
We will also value availability to travel because, although the bulk of the work is done in GMV's facilities in Madrid, travel for meetings or tests in European countries is necessary.
WHAT DO WE OFFER?
Hybrid
working model and 8 weeks per year of teleworking outside your usual geographical area.
Flexible start and finish times, and intensive working hours Fridays and in
summer.
Personalized
career plan development, training and language learning support.
National and international mobility.
Do you come from another country?
We can offer you a relocation package.
Competitive
compensation with ongoing reviews, adaptable compensation and
discount on brands.
Wellbeing
program: Health, dental and accident insurance; free fruit and coffee,
physical, mental and financialhealth training, and much more!
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Required Skill Profession
Engineers