Working for a fascinating semiconductor company, who is focused on RISC-V core IP development; within this team your responsibility will include, but is not limited to:
* Deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the system.
* Evaluate new IPs, driving new IP deployments as well as defining system-wide guidelines for IP requirements in the SoC.
* Closely drive resolution of issues and bugs gating the completion of the schedule.
Skills
* 5+ years of solid experience in IP / SoC design.
* Good understanding of ASIC design / verification / implementation flows.
* Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, and verification.
* Hands-on experience with SoC Design, Verilog RTL coding, and simulation software.
* General knowledge of synthesis, DFT, verification, formal verification, and silicon debug.
* Working knowledge with SystemVerilog or Verilog, C or C++, scripting languages such as Python.
* MUST HAVE - excellent communication skills (ideally in English / Spanish / Catalan).
Visa sponsorship and relocation support is available for highly skilled and relevant qualified engineers.
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