Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL
* Are you a Mid to Senior level Senior Verification Engineer looking for you next challenge?
* Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL?
* Want to join a very exciting Spain based semiconductor company?
If you can say to this, then please keep reading.
Were partnered with a genuinely exciting Barcelona HQd semiconductor organization and theyre seeking a number of Mid-to-Senior Verification Engineers to join them on a permanent basis, working fully onsite in central Barcelona.
Visa sponsorship is available if needed, plus free Spanish lessons to help you assimilate in Spain.
Required skills:
* MSc or PhD in a related field
* 4+ years relevant experience
* Proficiency in SystemVerilog and UVM
* Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
* Experience with simulation and simulation tools
* Knowledge of revision control methodology and tools (git, svn)
* Experience in block level and sub-system or top level verification
* Experience with formal and dynamic verification
* Strong problem-solving skills and attention to detail
* Excellent communication and teamwork abilities
Sound good?
In return youll receive an excellent yearly salary, flexible work schedules, and very good career progression, whilst working within a team of extremely talented individuals.
If this sounds interesting and youd like to learn more, click the link below to apply or email me with a copy of your resume on
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