Overview
Senior Verification Engineer – RISC-V | Barcelona (Relocation & Visa Sponsorship)
Are you a Senior Verification Engineer working on complex digital designs and high-performance CPUs – and feeling like your current role isn’t stretching you enough? This Barcelona-based semiconductor startup is developing high-performance RISC-V microprocessor cores for advanced AI and machine-learning applications. Verification is treated as a core discipline, and this role plays a critical part in taking designs from early architecture through multiple successful tape-outs.
As a Senior Verification Engineer, you’ll work in a modern UVM-based verification environment, verifying complex, coherent systems using SystemVerilog and industry-standard tools. You’ll collaborate closely with architecture and design teams, influence verification strategy, and take real ownership in a fast-moving startup environment where your work directly impacts silicon that ships.
The team is looking for engineers with strong experience in UVM, SystemVerilog, and scripting languages such as Python, Perl, Bash, or TCL, along with solid knowledge of revision control systems like Git or SVN. Exposure to formal verification is a plus. Experience with coherent systems and the CHI protocol, cache architectures, or PCIe and high-speed communication protocols will be particularly valuable.
The role is based in Barcelona, Spain, with a full relocation package and visa sponsorship available. To help you settle in, the company also offers Spanish lessons as part of the onboarding experience.
If you’re a Verification Engineer interested in working on cutting-edge RISC-V CPU architecture within a growing startup – even if you’re not actively job-hunting – this is a role worth exploring.
📩 Reach out to Steph Hutchinson at IC Resources for a confidential conversation.
Responsibilities
* Work in a modern UVM-based verification environment to verify complex, coherent systems using SystemVerilog.
* Collaborate with architecture and design teams to influence verification strategy.
* Take ownership of verification activities across design stages from early architecture to tape-outs.
* Contribute to verification plan development, coverage closure, and debug efforts to ensure robust silicon.
* Engage with high-speed interfaces and protocols as needed (e.g., CHI, PCIe, cache architectures).
Qualifications
* Strong experience in UVM, SystemVerilog, and scripting languages (Python, Perl, Bash, or TCL).
* Solid knowledge of version control systems (Git or SVN).
* Exposure to formal verification is a plus.
* Experience with coherent systems and high-speed communication protocols; familiarity with CHI protocol, cache architectures, or PCIe is valuable.
Benefits & Relocation
* Full relocation package and visa sponsorship.
* Spanish language lessons as part of onboarding.
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