Unlocking Innovation: A Senior ASIC Design Engineer Opportunity
We are seeking a highly experienced Senior ASIC Design Engineer to join our semiconductor team at the forefront of innovation.
This exceptional opportunity enables you to be part of a dynamic and multicultural team, working on cutting-edge SoC designs that will shape the future of AI, HPC, and other advanced technologies.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or a related field is required.
- Proven experience in 3+ successful tapeouts is essential.
- Proficiency in RTL design (Verilog/SystemVerilog) is a must.
- Experience in semiconductor IP design is necessary.
- Experience with TCL is required.
Please note that this position can also be based in Rome or Ghent.