PbCompany Description: /b /ppAistech Space is focused on generating affordable, recurrent, high-resolution thermal imagery of the planet to provide a new perspective of Earth’s changing resources. The company is based in Barcelona and aims to revolutionize remote sensing for environmental monitoring and resource management. /ppbr/ppbWhat you will do: /b /ppAistech Space is seeking an expert FPGA Design Engineer to lead the development of our next-generation image acquisition and processing payloads. You will be the architect of the \"digital brain\" of our systems, transforming raw high-speed sensor data into actionable insights using cutting-edge VHDL logic and hardware acceleration. /ppThis role is not just about writing code; it is about managing the entire data lifecycle—from the physical high-speed pins of the FPGA to the integration of AI engines and DMA streaming to memory. You will work at the intersection of hardware and high-level software, ensuring our systems are fast, synchronized, and reliable in demanding environments /ppIn this role, you are expected to work as a team, functioning as an agile, highly collaborative unit focused on short, client-driven development iterations. /ppYou will also be responsible for following internal standards and good practices in terms of project management, documentation, and time management, adopting an agile approach in your daily work. /ppbr/ppThe key objectives to be achieved in this position are: /pulliUnderstand Aistech Space mission objectives. /lilibXilinx RTL Development: /b Design and optimize modular VHDL code for Xilinx 7-Series, UltraScale+, and Versal Adaptive SoCs. /lilibHigh-Speed I/O Connectivity: /b Implement and debug high-speed transceivers (GTH/GTY) for protocols such as MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet. /lilibAdvanced Data Path: /b Architect low-latency data movement using AXI4-Stream, AXI SmartConnect, and Xilinx Video DMA (VDMA) or DataMover IPs. /lilibAI Engine Integration: /b Deploy and optimize neural networks using the Vitis AI flow, integrating DPU (Deep Learning Processor Unit) cores into the FPGA fabric. /lilibMemory Management: /bConfigure and optimize hardened DDR4/LPDDR4 memory controllers to handle multi-stream 4K/8K video buffering. /lilibTiming Closure: /b Author complex XDC constraints, manage multiple clock domains using MMCM/PLLs, and achieve timing closure on high-utilization designs. /lilibVerification Debug: /b Perform hardware-in-the-loop debugging using Vivado ILA (Integrated Logic Analyzer) and Vitis Analyzer. /liliWrite articles regarding different areas of interest to be published in our Aistech News magazine and on our website blog. /liliActively engage in the development of documentation to build out the company procedures and specification manuals. /liliFollow your curiosity to suggest new ideas to make our products and processes better. /li /ulpbr/ppbr/ppbWho you are: /b /ppbMust: /b /pulliDegree: BSc/MSc in Electronics, Telecommunications, or similar. /lilibVHDL Expert: /b Deep understanding of Xilinx-specific RTL optimization (utilizing DSP48 slices, Block RAM, and UltraRAM efficiently). /lilibAMD Toolchain Expert: /b Proficiency in Vivado Design Suite, Vitis Unified Software Platform, and Petalinux. /lilibIP Integration: /b Extensive experience with Xilinx IP Integrator and the AXI4 protocol family (Memory Mapped, Stream, and Lite). /lilibHigh-Speed Hardware: /bExperience with SerDes calibration, eye-diagram analysis, and high-speed PCB constraints. /lilibDMA/Data Transfer: /b Proven experience implementing Scatter-Gather DMA for high-bandwidth sensor data. /lilibVerification Skills: /b Experience with advanced simulation environments (UVVM, OSVVM, or UVM) and self-checking testbenches. /lilibSimulation: /b Experience with Xilinx Simulator (XSIM) or third-party tools like ModelSim/Questa using Xilinx Verification IP (VIP). /lilibScripting: /bProficiency in Tcl for Vivado automation and Python for data analysis. /liliFluent in English. /li /ulpbr/ppbr/ppbNice to have: /b /pullibVersal Experience: /b Knowledge of Versal AI Engines (AIE) and the Programmable Network on Chip (NoC). /lilibHLS Knowledge: /b Familiarity with Vitis HLS (C/C++ to RTL synthesis) for rapid IP development. /lilibSpace/High-Reliability Experience: /bFamiliarity with SEU (Single Event Upset) mitigation techniques and radiation-hardened design philosophies. /li /ulpbr/ppWhat You’ll Gain by Joining Us /p